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UT Tyler Department of Electrical Engineering Research

Dr. David Hoe FPGA Research

Field Programmable Gate Arrays (FPGAs) are complex logic devices which can be configured from a desktop personal computer. A state-of-the-art FPGA contains thousands of configurable logic blocks (CLBs). Each CLB will have several basic logic elements consisting of a look-up table (LUT) for implementing combinational logic and a memory element known as a flip-flop (FF). The wires connecting the various CLBs can be programmed as well through a series of switching boxes in the routing channels. A high-level descriptor language such as VHDL or Verilog is used to describe how an FPGA is to be configured.

Dr. David Hoe
The Floorplan of a Typical FPGA

The development costs of FPGAs are significantly lower than full custom integrated circuit designs. In addition, an FPGA design will often be more efficient in terms of power and speed than a microprocessor-based solution because an FPGA can be configured exactly to perform a desired function. A state-of-the-art FPGA is capable of implementing a sophisticated embedded processor, such as a 32-bit RISC design, on its reconfigurable fabric. Hence, the combination of low costs, superior performance, and logic flexibility make FPGAs the preferred design option for many modern applications.

Students working with Dr. Hoe
Students working on configuring a Xilinx Spartan 3 FPGA.

The SPEA Computer Engineering Laboratory has comprehensive research facilities for designing and testing of FPGAs. A couple recent research projects involving FPGAs include.

  • Random Number Generators
    The design of high-quality pseudo-random number generators (PRNGs) is important for many applications, from statistical physics simulators to secure encryption devices. My research has focused on the implementation of cellular automata on FPGAs for creating efficient PRNG designs. This has led to the development of an unique stream cipher design built on FPGAs. Much of this research has been carried out by undergraduate students.
  • Fault Tolerant Designs
    A fault tolerant circuit is capable of detecting an error and then correcting it. This has important applications in mission critical designs such as in avionics and medical electronic devices and for systems operating in remote and harsh environments such as outer space. Our recent work has demonstrated the feasibility of implementing fault tolerant arithmetic logic on FPGAs.

Representative FPGA Publications

D. H. K. Hoe, L. P. D. Bollepalli, and C. D. Martinez, "FPGA Fault Tolerant Arithmetic Logic: A Case Study Using Parallel-Prefix Adders," VLSI Design, Special Issue: FPGA-Based Architectures for High Performance Computing, Nov. 2013.

D. H. K. Hoe, J. M. Comer, J. C. Cerda, C. D. Martinez, M. V. Shirvaikar, “Cellular Automata-based Parallel Random Number Generators using FPGAs,” International J. of Reconfigurable Computing, (13 pages), 2012. (PDF)

L. Raut and D. H. K. Hoe, “Stream Cipher Design Using Cellular Automata Implemented on FPGAs,” IEEE 45th Southeastern Symposium on System Theory, pp. 146-149, March 2013. (PDF)

D. H. K. Hoe, “Introducing Multiple Soft Processor Cores Using FPGAs into the Computer Engineering Curriculum,” ASEE 2012 Annual Conference & Exposition, San Antonio, Session AC 2012-4159, June 2012. (PDF)

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